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DATA SHEET
MOS INTEGRATED CIRCUIT
PD8862
(2700 + 2700) PIXELS x 3 COLOR CCD LINEAR IMAGE SENSOR
DESCRIPTION
The PD8862 is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to electrical signal and has the function of color separation. The PD8862 has 3 rows of (2700 + 2700) staggered pixels, and each row has a dual-sided readout-type charge transfer register. And it has reset feed-through level clamp circuits and voltage amplifiers. Therefore, it is suitable for 600 dpi/A4 color image scanners, color facsimiles and so on.
FEATURES
* Valid photocell * Photocell pitch * Line spacing * Color filter * Resolution : (2700 + 2700) staggered pixels x 3 : 5.25 m : 63 m (12 lines) Red line - Green line, Green line - Blue line 10.5 m (2 lines) Odd line - Even line (for each color) : Primary colors (red, green and blue), pigment filter (with light resistance 10 lx*hour) : 24 dot/mm A4 (210 x 297 mm) size (shorter side) 600 dpi US letter (8.5" x 11") size (shorter side) * Drive clock level : CMOS output under 5 V operation * Data rate * Power supply * On-chip circuits : 6 MHz Max. : +12 V : Reset feed-through level clamp circuits Voltage amplifiers
7
ORDERING INFORMATION
Part Number Package CCD linear image sensor 22-pin plastic DIP (10.16 mm (400))
PD8862CY
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information.
Document No. S16033EJ3V0DS00 (3rd edition) Date Published July 2003 NS CP (K) Printed in Japan
The mark
shows major revised points.
2002
PD8862
BLOCK DIAGRAM
VOD 19 GND 11
2L
17
2
15
1
14
CCD analog shift register Transfer gate
D14 D66 D68 D70 S5400
13
D69
Transfer gate CCD analog shift register CCD analog shift register Transfer gate
D67 D14 D66 D68 D70 S5400
S2
VOUT1 20 (Blue)
******
Photocell (Blue)
D67
S5399
TG1 (Blue)
S1
12
D69
S2
VOUT2 21 (Green)
******
Photocell (Green) Transfer gate
CCD analog shift register CCD analog shift register Transfer gate
D67 D14 D66 D68 D70 S5400
S5399
TG2 (Green)
S1
10
D69
Transfer gate CCD analog shift register
3
2
4
S2
VOUT3 22 (Red)
******
Photocell (Red)
S5399
TG3 (Red)
S1
8
9
CLB RB
1L
2
1
2
Data Sheet S16033EJ3V0DS
PD8862
PIN CONFIGURATION (Top View)
CCD linear image sensor 22-pin plastic DIP (10.16 mm (400)) * PD8862CY
No connection Reset gate clock Reset feed-through level clamp clock Last stage shift register clock 1 No connection No connection No connection Shift register clock 2 Shift register clock 1 Transfer gate clock 3 (for Red) Ground
NC
1 2
22 21
VOUT3 VOUT2 VOUT1 VOD NC
Output signal 3 (Red) Output signal 2 (Green) Output signal 1 (Blue) Output drain voltage No connection Last stage shift register clock 2 No connection Shift register clock 2 Shift register clock 1 Transfer gate clock 1 (for Blue) Transfer gate clock 2 (for Green)
RB
1
1
CLB
1L
NC NC NC
3 4 5 6 7 8 9 10 11
1
20 19 18 17 16 15 14 13 12
Green
Blue
Red
2L
NC
2
2
1
1 TG1 TG2
5400
5400
GND
Caution Connect the No connection pins (NC) to GND.
5400
TG3
Data Sheet S16033EJ3V0DS
3
PD8862
PHOTOCELL STRUCTURE DIAGRAM
2.75 m
2.5 m
5.25 m
Channel stopper
Aluminum shield
PHOTOCELL ARRAY STRUCTURE DIAGRAM (Line spacing)
5.25 m 5.25 m 5.25 m Blue photocell array Blue photocell array
2 lines (10.5 m) 10 lines (52.5 m) 12 lines (63 m)
5.25 m 5.25 m 5.25 m
Green photocell array Green photocell array
2 lines (10.5 m) 10 lines (52.5 m) 12 lines (63 m)
5.25 m 5.25 m 5.25 m
Red photocell array Red photocell array
2 lines (10.5 m)
4
Data Sheet S16033EJ3V0DS
PD8862
ABSOLUTE MAXIMUM RATINGS (TA = +25C)
Parameter Output drain voltage Shift register clock voltage Reset gate clock voltage Reset feed-through level clamp clock voltage Transfer gate clock voltage Operating ambient temperature Storage temperature
Note
Symbol VOD V 1, V 2, V 1L, V 2L V RB V CLB
Ratings -0.3 to +15 -0.3 to +8 -0.3 to +8 -0.3 to +8 -0.3 to +8 0 to +60 -40 to +70
Unit V V V V
V TG1 to V TG3 TA Tstg
V C C
Note Use at the condition without dew condensation. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
RECOMMENDED OPERATING CONDITIONS (TA = +25C)
Parameter Output drain voltage Shift register clock high level Shift register clock low level Reset gate clock high level Reset gate clock low level Reset feed-through level clamp clock high level Reset feed-through level clamp clock low level Transfer gate clock high level Transfer gate clock low level Data rate V TG1H to V TG3H V TG1L to V TG3L f RB 4.75 -0.3 - V 1_H 0 2.0
Note
Symbol VOD V 1_H, V 2_H, V 1LH, V 2LH V 1_L, V 2_L, V 1LL, V 2LL V RBH V RBL V CLBH
Min. 11.4 4.75 -0.3 4.5 -0.3 4.5 -0.3
Typ. 12.0 5.0 0 5.0 0 5.0
Max. 12.6 5.5 +0.25 5.5 +0.5 5.5 +0.5 V 1_H
Note
Unit V V V V V V
V CLBL
0
V
V V MHz
+0.15 6.0
Note When Transfer gate clock high level (V TG1H to V TG3H) is higher than Shift register clock high level (V 1_H), Image lag can increase.
Data Sheet S16033EJ3V0DS
5
PD8862
ELECTRICAL CHARACTERISTICS
TA = +25C, VOD = 12 V, data rate (f RB) = 2 MHz, storage time = 5.5 ms, input signal clock = 5 Vp-p, light source : 3200 K halogen lamp + C-500S (infrared cut filter, t = 1 mm) + HA-50 (heat absorbing filter, t = 3 mm)
Parameter Saturation voltage Saturation exposure Red Green Blue Photo response non-uniformity Average dark signal Dark signal non-uniformity Power consumption Output impedance Response Red Green Blue Image lag Offset level
Note 1 Note 2
Symbol Vsat SER SEG SEB PRNU ADS DSNU PW ZO RR RG RB IL VOS td TTE RI Red Green Blue
Test Conditions
Min. 2.0 - - - - - - - - 4.15 3.66 2.36
Typ. 2.5 0.421 0.477 0.740 6 0.2 1.5 360 0.35 5.94 5.24 3.38 3.0 6.0 25 98 1.0 630 540 460 1666 2500 +300 1.0
Max. - - - - 20 2.0 5.0 540 1 7.73 6.82 4.39 7.0 7.5 - - 4.0 - - - - - +1000 -
Unit V lx*s lx*s lx*s % mV mV mW k V/lx*s V/lx*s V/lx*s % V ns % % nm nm nm times times mV mV
VOUT = 1.0 V Light shielding Light shielding
VOUT = 1.0 V
- 4.5 - 92 - - - - - - -2000 -
Output fall delay time
VOUT = 1.0 V, t1', t2' = 5 ns VOUT = 1.0 V, data rate = 6 MHz VOUT = 1.0 V
Total transfer efficiency Register imbalance Response peak
Dynamic range
Note 1
DR1 DR2
Vsat/DSNU Vsat/ CDS Light shielding Light shielding
Reset feed-through noise Random noise (CDS)
RFTN
CDS
Notes 1. Refer to TIMING CHART 2, 3. 2. When each fall time of 1L and 2L (t1', t2') is the Typ. value (refer to TIMING CHART 2, 3).
6
Data Sheet S16033EJ3V0DS
PD8862
INPUT PIN CAPACITANCE (TA = +25C, VOD = 12 V)
Parameter Shift register clock pin capacitance 1 Symbol C 1 Pin name Pin No. 9 14 Min. - - - 8 15 - - - 4 17 2 3 13 12 10 - - - - - - - Typ. Max. - - - - - - - - - - - - - Unit pF pF pF pF pF pF pF pF pF pF pF pF pF
1
250
250 500 250 250 500 10 10 10 10 100 100 100
1 total capacitance
Shift register clock pin capacitance 2 C 2
2
2 total capacitance
Last stage shift register clock pin capacitance C L
1L 2L RB CLB TG1 TG2 TG3
Reset gate clock pin capacitance Reset feed-through level clamp clock pin capacitance Transfer gate clock pin capacitance
C RB C CLB C TG
Remarks 1. 2.
Pins 9 and 14 ( 1), 8 and 15 ( 2) are each connected inside of the device. C 1 and C 2 show the equivalent capacity of the real drive including the capacity of between 1 and
2.
Data Sheet S16033EJ3V0DS
7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
VOUT1 to VOUT3
Optical black (49 pixels)
61 62 63 64 65 66
Valid photocell (5400 pixels)
Invalid photocell (4 pixels)
Invalid photocell (4 pixels)
Note Set the RB and CLB to high level during this period.
5466 5467 5468 5469 5470 5471
8
TIMING CHART 1-1 (Bit clamp mode, for each color)
TG1 to TG3
1, 1L
2, 2L
RB
Note
Data Sheet S16033EJ3V0DS
Note
CLB
PD8862
TIMING CHART 1-2 (Line clamp mode, for each color)
TG1 to TG3
1, 1L
2, 2L
RB
Note
Data Sheet S16033EJ3V0DS
Note
CLB
( TG1 to TG3)
5466 5467 5468 5469 5470 5471
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
VOUT1 to VOUT3
Optical black (49 pixels)
61 62 63 64 65 66
Valid photocell (5400 pixels)
Invalid photocell (4 pixels)
Invalid photocell (4 pixels)
Note Set the RB to high level during this period.
PD8862
Remark Inverse pulse of the TG1 to TG3 can be used as CLB.
9
PD8862
TIMING CHART 2 (Bit clamp mode, for each color)
t1 90% 10% 90% 10% t1' t2' t2
1 2
1L 2L
t5 90% 10% t7 t9 t3 t6 t4
90% 10% 90% 10% t5 t3 t6 t4
RB
t8 t10 t11
t7 t9
t8 t10 t11
CLB
RFTN
90% 10% td td
VOUT
RFTN VOS 10% 10%
Symbol t1, t2 t1', t2' t3 t4 t5, t6 t7 t8 t9, t10 t11
Min. 0 0 20 30 0 -5
Note
Typ. 25 5 100 150 25 25 100 25 25
Max. - - - - - - - - -
Unit ns ns ns ns ns ns ns ns ns
20 0 5
Note Min. of t7 shows that the RB and CLB overlap each other.
90%
RB
t7
CLB
90%
10
Data Sheet S16033EJ3V0DS
PD8862
TIMING CHART 3 (Line clamp mode, for each color)
t1 90% 10% 90% 10% t1' t2' t2
1 2
1L 2L
t5 90% 10% t3 t6 t4
90% 10% 90% 10% t5 t3 t6 t4
RB
CLB
"H"
RFTN RFTN
td
td
VOUT
VOS 10% 10%
Symbol t1, t2 t1', t2' t3 t4 t5, t6
Min. 0 0 20 30 0
Typ. 25 5 100 150 25
Max. - - - - -
Unit ns ns ns ns ns
Data Sheet S16033EJ3V0DS
11
PD8862
TG1 to TG3, 1, 2 TIMING CHART
t13 t12 t14
TG1 to TG3
90% 10% t15 90%
t16
1 2
t17
Note 1
t18
RB
90% t7
CLB (Bit clamp mode)
t22
t20
Note 2
t21
t23
CLB (Line clamp mode)
t9 t19 t10
Symbol t7 t9, t10 t12 t13, t14 t15, t16 t17, t18 t19 t20, t21 t22, t23
Min. -5
Note 3
Typ. 25 25 10000 50 1000 400 t12 50 350
Max. - - 50000 - - - 50000 - -
Unit ns ns ns ns ns ns ns ns ns
0 5000 0 900 200 t12 0 0
Notes 1. Set the RB and CLB to high level during this period. 2. Set the RB to high level during this period. 3. Min. of t7 shows that the RB and CLB overlap each other.
90%
RB
t7
CLB
90%
Remark Inverse pulse of the TG1 to TG3 can be used as CLB.
12
Data Sheet S16033EJ3V0DS
PD8862
1, 2 cross points
1
1.0 V to 4.0 V 1.0 V to 4.0 V
2
1, 2L cross points
1
2.0 V or more 0.5 V or more
2L
2, 1L cross points
2
2.0 V or more 0.5 V or more
1L
Remark Adjust cross points ( 1, 2), ( 1, 2L) and ( 2, 1L) with input resistance of each pin.
Data Sheet S16033EJ3V0DS
13
PD8862
DEFINITIONS OF CHARACTERISTIC ITEMS
1. Saturation voltage : Vsat Output signal voltage at which the response linearity is lost. 2. Saturation exposure : SE Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage occurs. 3. Photo response non-uniformity : PRNU The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of uniform illumination. This is calculated by the following formula.
PRNU (%) =
x x 100 x
x : maximum of xj - x
5400 j=1
xj
x=
5400
xj : Output voltage of valid pixel number j
VOUT
Register Dark DC level
x
x
4. Average dark signal : ADS Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula.
5400 j=1
dj
dj : Dark signal of valid pixel number j
ADS (mV) =
5400
14
Data Sheet S16033EJ3V0DS
PD8862
5. Dark signal non-uniformity : DSNU Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. This is calculated by the following formula.
DSNU (mV) : maximum of dj - ADS j = 1 to 5400 dj : Dark signal of valid pixel number j
VOUT ADS Register Dark DC level DSNU
6. Output impedance : ZO Impedance of the output pins viewed from outside. 7. Response : R Output voltage divided by exposure (lx*s). Note that the response varies with a light source (spectral characteristic). 8. Image lag : IL The rate between the last output voltage and the next one after read out the data of a line.
TG
Light ON OFF
VOUT V1 VOUT
IL (%) =
V1 x 100 VOUT
Data Sheet S16033EJ3V0DS
15
PD8862
9. Register imbalance: RI The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the average output voltage of all the valid pixels.
n
2 n RI (%) =
j=1
(V2j -1 - V2j)
1 n
j=1
2
Vj
n : Number of valid pixels Vj : Output voltage of each pixel
n
x 100
10. Random noise (CDS) : CDS Random noise CDS is defined as the standard deviation of a valid pixel output signal with 100 times (=100 lines) data sampling at dark (light shielding). CDS is calculated by the following procedure. 1. One valid photocell in one reading is fixed as measurement point. 2. The output level is measured during the reset feed-through period which is averaged over 100 ns to get "VDi". 3. The output level is measured during the video output time averaged over 100 ns to get "VOi". 4. The correlated double sampling output is defined by VCDSi = VDi - VOi 5. Repeat the above procedure (1 to 4) for 100 times (= 100 lines). 6. Calculate the standard deviation CDS using the following equation.
100
CDS (mV) =
i=1
(VCDSi - V)
100
2
, V=
1
100
100 i = 1
VCDSi
Reset feed-through
Video output
16
Data Sheet S16033EJ3V0DS
PD8862
STANDARD CHARACTERISTIC CURVES (Reference Value)
DARK OUTPUT TEMPERATURE CHARACTERISTIC
8 2
STORAGE TIME OUTPUT VOLTAGE CHARACTERISTIC (TA = +25C)
4
Relative Output Voltage
2
1
0.5
Relative Output Voltage
10 20 30 40 50
1
0.25
0.2
0.1 0
0.1
1
5 Storage Time (ms)
10
Operating Ambient Temperature TA (C)
TOTAL SPECTRAL RESPONSE CHARACTERISTICS (without infrared cut filter and heat absorbing filter) (TA = +25C)
100 R
B 80
G
Response Ratio (%)
60
40
G 20
B 0 400 500 600 Wavelength (nm) 700 800
Data Sheet S16033EJ3V0DS
17
PD8862
APPLICATION CIRCUIT EXAMPLE
+12 V +5 V 10 F/16 V +
PD8862
0.1 F 1 47 47 150 2 3 4 5 6 7 4.7 4.7 10 8 9 10 11 NC VOUT3 VOUT2 VOUT1 VOD NC 22 21 20 19 18 17 16 15 14 13 12 4.7 4.7 10 10 150 B3 B2
+
0.1 F 47 F/25 V
RB CLB
RB
CLB 1L
NC NC NC
+5 V B1
1L
+
2L
NC
0.1 F 10 F/16 V
2L
2
2
2 1 TG1 TG2
1 TG3
GND
1 TG
Caution Connect the No connection pins (NC) to GND. Remarks 1. The inverters shown in the above application circuit example are the 74HC04 (data rate < 2 MHz) or the 74AC04 (2 data rate < 6 MHz). 2. Inverters B1 to B3 in the above application circuit example are shown in the figure below.
B1 to B3 EQUIVALENT CIRCUIT
+12 V + 47 F/25 V
100 CCD VOUT 100 2SC945 2 k
18
Data Sheet S16033EJ3V0DS
PD8862
PACKAGE DRAWING
PD8862CY CCD LINEAR IMAGE SENSOR 22-PIN PLASTIC DIP (10.16 mm (400) )
(Unit : mm)
44.00.3 1st valid pixel 6.360.3 22
1
9.250.3 12
1 37.5
11 2.0 10.160.2
1.020.15
4.390.4
(1.72)
2
2.620.2 0.460.1 2.540.25 (5.42) 4.210.5
3
0.250.05 10.16 +0.7 -0.2
Name Plastic cap
Dimensions 42.9x8.35x0.7
Refractive index 1.5
1 1st valid pixel The center of the pin1 2 The surface of the CCD chip The top of the cap 3 The bottom of the package The surface of the CCD chip
22C-1CCD-PKG12-2
Data Sheet S16033EJ3V0DS
19
PD8862
RECOMMENDED SOLDERING CONDITIONS
When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. Type of Through-hole Device
PD8862CY : CCD linear image sensor 22-pin plastic DIP (10.16 mm (400))
Process Partial heating method Conditions Pin temperature : 300 C or below, Heat time : 3 seconds or less (per pin)
Cautions 1. 2.
During assembly care should be taken to prevent solder or flux from contacting the plastic cap. The optical characteristics could be degraded by such contact. Soldering by the solder flow method may have deleterious effects on prevention of plastic cap soiling and heat resistance. So the method cannot be guaranteed.
20
Data Sheet S16033EJ3V0DS
PD8862
NOTES ON HANDLING THE PACKAGES
1 DUST AND DIRT PROTECTING
The optical characteristics of the CCD will be degraded if the cap is scratched during cleaning. Don't either touch plastic cap surface by hand or have any object come in contact with plastic cap surface. Should dirt stick to a plastic cap surface, blow it off with an air blower. For dirt stuck through electricity ionized air is recommended. And if the plastic cap surface is grease stained, clean with our recommended solvents.
CLEANING THE PLASTIC CAP
Care should be taken when cleaning the surface to prevent scratches. We recommend cleaning the cap with a soft cloth moistened with one of the recommended solvents below. Excessive pressure should not be applied to the cap during cleaning. If the cap requires multiple cleanings it is recommended that a clean surface or cloth be used.
RECOMMENDED SOLVENTS
The following are the recommended solvents for cleaning the CCD plastic cap. Use of solvents other than these could result in optical or physical degradation in the plastic cap. Please consult your sales office when considering an alternative solvent. Solvents Ethyl Alcohol Methyl Alcohol Isopropyl Alcohol N-methyl Pyrrolidone Symbol EtOH MeOH IPA NMP
2 MOUNTING OF THE PACKAGE
The application of an excessive load to the package may cause the package to warp or break, or cause chips to come off internally. Particular care should be taken when mounting the package on the circuit board. Don't have any object come in contact with plastic cap. You should not reform the lead frame. We recommended to use a IC-inserter when you assemble to PCB. Also, be care that the any of the following can cause the package to crack or dust to be generated. 1. Applying heat to the external leads for an extended period of time with soldering iron. 2. Applying repetitive bending stress to the external leads. 3. Rapid cooling or heating
3 OPERATE AND STORAGE ENVIRONMENTS
Operate in clean environments. CCD image sensors are precise optical equipment that should not be subject to mechanical shocks. Exposure to high temperatures or humidity will affect the characteristics. So avoid storage or usage in such conditions. Keep in a case to protect from dust and dirt. Dew condensation may occur on CCD image sensors when the devices are transported from a low-temperature environment to a high-temperature environment. Avoid such rapid temperature changes. For more details, refer to our document "Review of Quality and Reliability Handbook" (C12769E)
4 ELECTROSTATIC BREAKDOWN
CCD image sensor is protected against static electricity, but destruction due to static electricity is sometimes detected. Before handling be sure to take the following protective measures. 1. Ground the tools such as soldering iron, radio cutting pliers of or pincer. 2. Install a conductive mat or on the floor or working table to prevent the generation of static electricity. 3. Either handle bare handed or use non-chargeable gloves, clothes or material. 4. Ionized air is recommended for discharge when handling CCD image sensor. 5. For the shipment of mounted substrates, use box treated for prevention of static charges. 6. Anyone who is handling CCD image sensors, mounting them on PCBs or testing or inspecting PCBs on which CCD image sensors have been mounted must wear anti-static bands such as wrist straps and ankle straps which are grounded via a series resistance connection of about 1 M.
Data Sheet S16033EJ3V0DS
21
PD8862
[MEMO]
22
Data Sheet S16033EJ3V0DS
PD8862
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Data Sheet S16033EJ3V0DS
23
PD8862
* The information in this document is current as of July, 2003. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above).
M8E 02. 11-1

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